Flash memories are assembled in solid state drives (SSDs) and provide fast and large-capacity storage that replaces hard disk drives (HDDs). In an SSD, a controller chip, a cache memory chip (e.g., dynamic random access memory, or DRAM) and multiple flash memory chips are built. The number of times that each memory element in a flash memory can be rewritten is limited. To maintain data retention capability, the controller chip performs operations, such as wear leveling and write caching.
To operate these reliability maintenance systems mentioned above, it is necessary for the SSD to include a large-capacity cache memory. Meanwhile, the cache memory built in the SSD and the DRAM used for calculation by the processor are redundant. Therefore, an embedded type SSD has been proposed in which the DRAM for the processor acts as the cache memory for the SSD. However, there is a drawback that, when a cache operation is performed on a large amount of information to be recorded, the processing speed of the processor is reduced. Accordingly, development is desired of a so-called unified memory that is capable of operating as a volatile memory even though the memory is physically a non-volatile large capacity memory.